ENTITY processeur IS
  PORT (
  ck      : in BIT;
  reset   : in BIT;
  req     : out BIT;
  gnt     : in BIT;
  vdd     : in BIT;
  vss     : in BIT
  );
END processeur;

-- Architecture Declaration

ARCHITECTURE VBE OF processeur IS
  SIGNAL reg_etat   : REG_VECTOR(2 downto 0) REGISTER;
  SIGNAL sig_etat   : BIT_VECTOR(2 downto 0);

BEGIN
  sig_etat(0)   <= (reg_etat(2) OR (reg_etat(0) AND NOT(gnt)));
  sig_etat(1)   <= (reg_etat(0) AND gnt);
  sig_etat(2)   <= reg_etat(1);
  label0 : BLOCK ((NOT((ck'STABLE)) AND ck) = '1')
  BEGIN
  reg_etat(0) <= GUARDED (sig_etat(0) OR reset);
  reg_etat(1) <= GUARDED (sig_etat(1) AND NOT(reset));
  reg_etat(2) <= GUARDED (sig_etat(2) AND NOT(reset));
  END BLOCK label0;
  req   <= (reg_etat(0) OR reg_etat(1));
END;